The present invention relates to Integrated Circuits (IC), and more particularly to a high-frequency clock interconnect circuit used in ICs.
An IC often includes a clock interconnect circuit adapted to generate a multitude of clock signals that control the operations of the various blocks disposed in the IC. Controlling the variation in the arrival times of the clock signals, commonly referred to as clock skew, is important.
Clock skew is dependent on two main parameters, namely the loading seen by the clock signal, as well as the RC delay of the clock interconnect. As is well known, clock skew increases the cycle times and reduces the rate at which the IC can operate. A number of different clock drivers have been developed to compensate for the differential delays of individual clock signals in order to minimize clock skew.
As the operating frequency of an IC increases, the power consumption of various components of a clock distribution circuit, such as the local oscillator (LO) and the phase locked-loop (PLL), starts to increase. To reduce the power consumption at high frequencies, current-mode clock drivers/buffers have been developed. Conventional current-mode clock drivers, however, are designed to operate under worst case voltage, temperature and process conditions. As such, conventional current-mode buffers are not power efficient. Controlling the power consumption of a clock interconnect circuit operating at relatively high frequencies remains a challenge.